What’s the difference between create_design_definition and define_designs?
define_designs automatically creates a module with def as design based on the given Verilog and def; create_design_definition creates a design for the specified module in the absence of some sub design def.
For hierarchical design, if no DEF files provided, user needs to create design definition manually:
xtop> create_design_definition-name A -verilogs a.v
xtop> create_design_definition-name B -verilogs b.v
xtop> import_designs
How to check if the design is ready for legalization?
Use the report_design_file_status command, to check if the verilog and DEF files are imported successfully.
xtop > report_design_file_status
Design : cpu
Verilog : succeeded
/.../tutorial/input_files/design_data/cpu.v.gz
DEF : succeeded
/.../tutorial/input_files/design_data/cpu.def.gz
How to check if the linked timing library files are complete for current design?
Use the report_timing_library_file_status command, to check if the timing library files are read in successfully.
xtop > report_timing_library_file_status
Corner: fast
/.../tutorial/input_files/lib/tutoriallvtbc.idb : succeeded
Corner: slow
/.../tutorial/input_files/lib/tutoriallvtwc.idb : succeeded
How to check if the linked LEF files are complete for current design?
Use the report_reference_library_file_status command, to check if the LEF files are linked successfully.
xtop > report_reference_library_file_status
/.../tutorial/input_files/lef/tutorial.lef : succeeded
Warnings : 1
Warning(line: 674-734) : Cumulative Antenna ratios already set with different value.
Why does XTop report error when importing UPF file?
Maybe region_file is not given correctly.
xtop> import_power_domain -design TOP \
-upf_file {/.../data/test.upf} -region_file {/.../data/top.pd}
How to create a multiple voltage design when there is no UPF file？
User is allowed to only import region file when there is no UPF file. However, an UPF file is highly recommended.
xtop> import_power_domain -design TOP \
-region_file {/home/user/design/data/top.pd}
If the design version is inconsistent with the timing version, can you continue?
1) First of all, no matter what changes have been made to design, it is not recommended to continue.
2) If only the size of the cell will affectthe accuracy of the timing before and after the cell
3) If the buffer is inserted, the timing propagation may be broken, which may result in inaccurate timing during the fix timing.
How to use the dont_touch list script before using sub block in Top flatten design？
Since there is less hier path in the dont_touch list of the sub block, it cannot be used directly.
After switching the hier path through current_instance, you can directly source the dont_touch list of the sub block. After running, return to top with the current_instance command.
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