module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
always@(posedge KEY[0])begin
LEDR<=KEY[1]?SW:{LEDR[2]^LEDR[1],LEDR[0],LEDR[2]};
end
endmodule
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
always@(posedge clk)begin
if(reset) q<=32'h1;
else q<={q[0],q[31-:9],q[22]^q[0],q[21:3],q[2]^q[0],q[1]^q[0]};
end
endmodule
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
wire [3:0] q;
always@(posedge clk)begin
if(~resetn) q<=4'h0;
else begin
q[3]<=q[2];
q[2]<=q[1];
q[1]<=q[0];
q[0]<=in;
end
end
assign out = q[3];
endmodule
