How to calculate bottleneck for timing inspection?

Data Path:

-Hold

  ∑min(-holdslack,Setup margin x Worst(bufferMin/Maxratio))

-Setup

  |CellA|-----Net------|CellB|

  (CellA_delay*0.5 + Net_delay*0.3 + CellB_delay*0.2) * path_number

Clock Path：

  |Launch Violation path# - Capture Violation path#| - common path (both launch and capture)

- Transition：The number of violations on this fanout

- Maxfanout/cap/long wire：Violation value

What does the delay changes of each candidate represent for in eco action widget?

It will evaluate the changes that will be made to the setup and hold after completing an eco operation according to the pin of the selected cell. 

The effects of different names of pins in different locations may be different.

How to read the summary after a manual eco action?

1. Check whether the cell of the eco action is legal;

2. Whether the operation of the eco is beneficial to improve the timing;

3. Whether the other timing becomes worse.

How to achieve the slack eco process on the pin?

GBA mode:

If the path slack exist, use the path slack, otherwise, use the gba slack.

Path mode:

Only the violation on the fixing path as slack; take the GBA mode number as margin.

Why do nothing when optimizing the leakage by downsize?

1) Most of fail reason is CREATE_GS_SOLVER_FAILED, and some are no_margin. Others don’t touch can be ignored first.

2) Looked at the group information iscorrect, the cells of different driver strength are assigned to a group, which proves that there is a replaceable cell.

3) It is suspected that the cap calculationis too pessimistic and the margin is not enough, but it is not possible to change one. So put the setup margin set loose and try again or do nothing, prove not a problem with margin.

4) CREATE_GS_SOLVER_FAILED This reason can be understood as a non-replaceable cell. Since the grouping is correct, it is possible that the cells in the group are not available and are used by don’t. Checked the don’t use setting and found that the ULVT cell is really disabled. This design only has a ULVT cell, so you can't do downsize.You can remove this don’t use.

When XTop uses the gba mode to do setup/hold fix (with path data), is it possible that the previous TE repairs the break setup?

Mainly depends on the reasons for the Break setup. Generally speaking, there are two kinds of reasons: 

1. Calculating the accuracy problem. Regardless of whether it is caused by SI or other reasons, there will always bedifferences with the results of PT, but from the current data,XTop is better. In other words, in the same example, XTop will break setup less than ICE.

2. Timing transfer algorithm. If the breaksetup is a lot, it is often caused by this reason. Because there is nodistinction betweenrise_slack and fall_slack in ICE, this problem is more likely to occur. The XTop has improved the timing transfer algorithm, and rise_slack and fall_slack are passed separately, so it is estimated that more than 90% of similar problems can be eliminated. However, in theory, there are no solutions to the timing transfer algorithm bug caused by commands such as multi_clock, set_false_path, andset_max_delay. We have chosen a theoretically buggy algorithm for timing optimization. The biggest reason is that it can only reduce the timing transfer time brought by a large number of ECOs. From the current point of view, it encounters the timing transfer caused by SDC. The probability of a bug is still very low, almost never encountered.

Why does eco cause a fill1 gap between eco cells?

You can avoid this problem by defining at least 0.28 at the beginning of lef and adding an edge type rule to each cell;

PROPERTYDEFINITIONS

LIBRARY LEF58_CELLEDGESPACINGTABLE STRING "CELLEDGESPACINGTABLE EDGETYPE grp1 grp1EXCEPTABUTTED  0.28 ; " ;

LIBRARY LEF58_MAXVIASTACK STRING "MAXVIASTACK 4 NOSINGLE RANGE M1 M6  ;" ;

LAYER LEF58_CUTCLASS STRING ;

LAYER LEF58_ENCLOSURE STRING ;

LAYER LEF58_ENCLOSUREEDGE STRING ;

...

MACRO LEF58_EDGETYPE STRING ;

END PROPERTYDEFINITIONS

MACRO AN2D0BWP30P140

...

CLASSCORE ;

SITEcore ;

PROPERTYLEF58_EDGETYPE "

EDGETYPELEFT grp1 ;

EDGETYPERIGHT grp1 ;   " ;

PIN ...

Why is the break setup caused by the fix hold on 7nm?

Because the size of the cell will be down to D1 when fix hold, but the driver capability of D1 is very weak, so it will produce a serious SI problem.

It is recommended that the library under theadvanced technology or low-voltage, let the customer give the don't_use between the cells of D1 ~ D2 in the fix hold size cell:

xtop> set_dont_touch [get_lib_cells*D1BWP*]

How to use the data of the top session to repair two sub sys modules?

1) When writing data from the top session, it must be written out.

2) When creating design in XTop, you can only give verilog and DEF of Top and two sub sys to be repaired. All other modules are given to LEF. If there is no LEF, all the verilogs of other modules are given, but you can not give the DEFs. Other modules can be treated as black boxes if there is no timing lib, so there is usually no problem.

3) Then you can fix it directly.

Why is there no effect when using set_dont_touch [get_paths -group xxx]?

The command to use set_dont_touch [get_paths -group xxx] is to skip some clock domains in the fix. This operation is mainly to implement the function of the previous TE's ice_set_parameter opt.skip_clock_groups, but the reason why it cannot be implemented is that it is now GBA signoff and fix, did not write path out, so can not achieve the above dont_touch settings

The reason why this function of TE is not supported is that GBA does not have the concept of clock group. The original ICE can be said to be wrong, because it is impossible to have only one clock onone pin. When developing a new version, the initial feedback from the client isthat the old ICE clock group can't be used, let XTop support the path to skip. The current behavior is more reasonable.

When fix_si_violation, is the buffer used the first one in the setup buffer list？

The option described in the option is buffer instead of buffer_list.

If it is not specified in the buffer option, it will go to the first one defined in the parameter eco_buffer_list_for_setup.

What should pay attention to when it is sizedown in advanced technology?

XTop is recommended to disable the D1 cell in the size down of the advanced process, otherwise it is easy to cause SI or the setup is broken due to the large transition. If the customer can accept the break, you can not disable it, and then repair it back in the next version. If the customer is sensitive to this, it is recommended to explain to the customer that D1 is banned.

Why timing path not fixed between module and other IP?

When the module is repaired by the top layer, it was found that the path timing between the module and other IPs was not repaired, and some paths in the PT were lost in XTop.

Reason:

The related_pin name of the IP DB file and the LIB file port are not uniform. As a result, when XTop goes to read STA data, the clock pin of the start pin on the PATH cannot be found, resulting in path loss.

Solution:

For the ETM process, you need to add the "set extract_model_lib_format_with_check_pin true" command when extracting the timing lib script to unify the DB and LIB names.

For the QTM process, when creating the timing arc using the create_qtm_timing_arc command, the edge should be set separately -from_edge/-to_edge.

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